Memory card design with parity and ECC for non-parity and non-ECC systems
US6185718A · kind A · utility
66Cited by
18References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory card design which adds parity for non-parity computer systems to supply error detection capabilities is provided. The apparatus includes a memory card, parity DRAM locatable on the memory card, logic for generating and checking parity bits and logic for the control of the generating, checking and storing parity bits. Also, in another embodiment, the apparatus adds error correction code to the memory card to provide error detection and correction code to systems lacking such capabilities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.