Techniques for maintaining alignment of cut dies during substrate dicing
US6187654A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Sep 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68313
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A nest arrangement which is configured to support a substrate during a dicing process, and methods for using such a nest arrangement, are disclosed. According to one aspect of the present invention, a nest arrangement supports a substrate, which includes a first side and a second side, the first side being smoother than the second side. This nest arrangement includes a nest having a first side and a second side disposed above a vacuum retainer plate. The nest includes a locator pin for aligning the substrate with the nest when said substrate is disposed on the first side of the nest, and has a grid which defines at least one nest opening with an opening area that is smaller than an area of a chip diced from the substrate, and at least one retainer wall disposed on the first side proximate the opening area. The vacuum retainer plate has thereon at least one vacuum pedestal, which is configured to be disposed through the nest opening when the nest is mated with the vacuum retainer plate. The vacuum pedestal protrudes above the first side of the nest when the vacuum pedestal is disposed through the nest opening to lift the substrate off the first side of the nest when the nest is mate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.