Power-on-reset logic with secure power down capability
US6188257A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 1999 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Feb 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/554
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.