Reducing impact of coupling noise
US6188598A · kind A · utility
18Cited by
6References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1999 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a first bitline pair 310 on a first bitline level which is adjacent to a second bitline pair 320 on a second bitline level is provided. The first bitline pair comprises m twists 340, where m is a whole number.gtoreq.1 and the second bitline pair comprises n twists 350 and 351, where n is a whole number .noteq.m. The twists transform coupling noise from adjacent bitline pairs into common mode noise, which results in improved signal margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.