Reundancy circuit for semiconductor memories
US6188617A · kind A · utility
4Cited by
2References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Jul 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy circuit for semiconductor memories having word lines organized in segments. If a defective word line appears in a segment then, by virtue of inter-segment redundancy, a redundant word line in the same or in a different segment can be activated by a segment select signal. Fuse sets assigned to the respective segments provide output signals. The segment select signal is generated directly by evaluating the fuse set output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.