Patent · US Expired

Integrated memory having column decoder for addressing corresponding bit line

US6188642A · kind A · utility

52Cited by

4References

5Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Sabine Schoniger · Hersbruck, DE
Peter Schrogmeier · Hersbruck, DE
Thomas Hein · Hersbruck, DE
Stefan Dietrich · Potsdam, DE
Thilo Marx · Villingen-Schwenningen, DE

Key dates

Filing date	Jul 6, 1999
Grant date	Feb 13, 2001
Priority date	—
Expiry date	Jul 6, 2019

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.