Peter Schrogmeier
29Patents
8h-index
15Co-inventors
68Inventor score
Filing activity: Mar 1, 1999 → May 5, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6614700B2 | Circuit configuration with a memory array | Physics | 68 | Expired |
| US6687669B1 | Method of reducing voice signal interference | Physics | 58 | Expired |
| US6188642A | Integrated memory having column decoder for addressing corresponding bit line | Physics | 52 | Expired |
| US6804165B2 | Latency time switch for an S-DRAM | Physics | 14 | Expired |
| US7031421B2 | Method and device for initializing an asynchronous latch chain | Physics | 12 | Expired |
| US6351419B1 | Integrated memory with a block writing function and global amplifiers requiring less space | Physics | 12 | Expired |
| US6401224B1 | Integrated circuit and method for testing it | Physics | 9 | Expired |
| US6272035A | Integrated memory | Physics | 9 | Expired |
| US6388944B2 | Memory component with short access time | Physics | 6 | Expired |
| US6275445A | Synchronous integrated memory | Physics | 6 | Expired |
| US6882554B2 | Integrated memory, and a method of operating an integrated memory | Physics | 5 | Expired |
| US6480024B2 | Circuit configuration for programming a delay in a signal path | Electricity | 5 | Expired |
| US6101141A | Integrated memory | Physics | 4 | Expired |
| US6144590A | Semiconductor memory having differential bit lines | Physics | 4 | Expired |
| US6310824A | Integrated memory with two burst operation types | Physics | 3 | Expired |
| US7120818B2 | Method and device for data transfer | Physics | 3 | Expired |
| US7363561B2 | Method and circuit arrangement for resetting an integrated circuit | Electricity | 3 | Expired |
| US6359832B2 | Method and circuit configuration for read-write mode control of a synchronous memory | Physics | 3 | Expired |
| US6285605A | Integrated memory having redundant units of memory cells, and test method for the redundant units | Physics | 3 | Expired |
| US7058840B2 | Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock | Electricity | 1 | Expired |
| US6028815A | Integrated memory | Physics | 1 | Expired |
| US6396755B2 | Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory | Physics | 1 | Expired |
| US6437410B1 | Integrated memory | Physics | 1 | Expired |
| US6385123B1 | Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated | Physics | 1 | Expired |
| US6256219A | Integrated memory having memory cells disposed at crossover points of word lines and bit lines | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.