System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency
US6189078A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device. A purge command is issued to the first device to invalidate the copy of the requested data segment in the first local memory. Upon issuance of the purge command to the first device, a purge acknowl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.