Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layer
US6190975A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1998 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Dec 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.