Method for fabricating of super self-aligned bipolar transistor
US6190984A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 13, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Jan 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/021
Abstract
The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.