Method of forming trench isolation structure
US6191002A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Apr 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a trench isolation structure is provided, which prevents generation of defects such as voids, cracks, and depressions of an isolation dielectric formed in an isolation trench without problems such as isolation region expansion, isolation capability degradation, and current leakage increase. In a first step, an isolation trench is formed in a semiconductor substrate to expose a top of the trench from a main surface of the substrate. In a second step, the whole main surface of the substrate is covered with a solution of a silazane perhydride polymer by spin coating, thereby forming a film of the solution covering the whole main surface of the substrate. The trench is entirely filled with the film of the solution. The film of the solution may be formed directly on the main surface of the substrate or formed indirectly over the main surface of the substrate via any intervening film or films. In a third step, the film of the solution covering the main surface of the substrate is converted to an oxide film of silicon covering the main surface of the substrate due to chemical reaction. In a fourth step, the oxide film of silicon covering the main surface of the substra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.