Method of forming a multi-layered dual-polysilicon structure
US6191017A · kind A · utility
26Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Apr 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of forming a multi-layered dual-polysilicon structure that forms a polysilicon gate prior to formation of an ion implantation barrier and that requires fewer steps, is more economical, and permits fabrication of more compact semiconductor circuits and devices than prior art methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.