Interlayer dielectric with a composite dielectric stack
US6191050A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | May 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, a phosphorous doped oxide layer is deposited on the semiconductor device to fill gaps and provide phosphorous for gettering. Then, an undoped oxide layer is deposited and planarized using chemical mechanical polishing (CMP). The undoped oxide layer is denser than the phosphorous doped oxide layer, so the undoped oxide layer can be polished more uniformly than the phosphorous doped oxide layer and can serve as a polish stop for a subsequent tungsten plug polish. Also, the denser undoped oxide layer serves as a more effective moisture barrier than the doped oxide layer. Overall fabrication process complexity can be reduced by performing both oxide depositions in a single operation with no intervening densification or CMP steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.