Package structure for low cost and ultra thin chip scale package
US6191483A · kind A · utility
16Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Thin organic layers are laminated on both the top and bottom of a relatively thin ceramic layer to form a reliable thinner composite substrate for packaging a chip-scale flip-chip die in a thin package. A semiconductor die has a number of solder bump-mounting pads formed thereupon which are connected with solder bumps to mounting pads on the top surface of the thin composite substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.