Power factor compensation controller
US6191565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2000 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | May 5, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power factor compensation controller for use in a switching power supply having a switch, an inductor, and upper and lower reference signals that are proportional to an input voltage to the switching power supply includes a multiplier that multiplies an error signal and a signal representative of a current in the switch to produce a multiplier output signal. The power factor compensation controller further includes an adder that adds the multiplier output signal to the lower reference signal to produce an adder output signal and a comparator that compares the adder output signal to the upper reference signal to produce a comparator output signal. The power factor compensation controller also includes a flip-flop that receives the comparator output signal and a clocking signal and a logic gate that receives an output of the flip-flop and the clocking signal to produce a gating signal for controlling the conduction of the switch so that an envelope of peak currents in the switch is substantially in-phase with the input voltage to the switching power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.