Method and apparatus for reducing standby leakage current using input vector activation
US6191606A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1998 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Sep 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.