Balanced loss driver circuit including high-side/low-side MOS switches
US6191625A · kind A · utility
8Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Mar 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/0806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A driver circuit having series-connected high-side and low-side MOS switches with MOS transistors for driving a load, a temperature-limiting circuit and a current-limiting circuit, which is assigned to one of the two MOS transistors. In order to balance power losses between the high-side and low-side MOS switches, provision is made for the gate of the MOS transistor without the current-limiting circuit to be connected to ground via a voltage generator, whose voltage corresponds to a maximum drive voltage for this MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.