Single-poly non-volatile memory cell having low-capacitance erase gate
US6191980A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | May 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.