Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel.
US6191997A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a burst operation, a counter (18) receives one or more bits of a starting column address. The count signal (A[2:1]) generated by the counter is provided to an address adder (20). The address adder generates column address bits (B[2:1]) for a column to be selected in the burst operation. The Y-decoder circuitry (16.0,16.1) selects an even column and an odd column in parallel. The count address bits (A[2:1]) are used as address bits for the even column, and the address bits (B[2:1]) generated by the address adder are used as address bits for the odd column, or vice versa. The even and odd columns can be at non-consecutive column addresses, or they can be at consecutive column addresses starting at an odd column address boundary. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories. Some embodiments are suitable for double data rate memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.