Programmable logic device memory array circuit having combinable single-port memory arrays
US6191998A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Dec 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable single-port memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.