High performance cache directory addressing scheme for variable cache sizes utilizing associativity
US6192458A · kind A · utility
47Cited by
10References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 23, 1998 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Mar 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To avoid multiplexing within the critical address paths, the same address field is employed as a index to the cache directory and cache memory regardless of the cache memory size. An increase in cache memory size is supported by increasing associativity within the cache directory and memory, for example by increasing congruence classes from two members to four members. For the smaller cache size, an additional address "index" bit is employed to select one of multiple groups of address tags/data items within a cache directory or cache memory row by comparison to a bit forced to a logic 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.