Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices
US6193870A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1997 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | May 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.