Method of dual damascene etching
US6194128A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Sep 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel method of dual damascene etching is disclosed. It is shown that the performance of ULSI circuits can be improved by shrinking interconnect dimensions through the use of dual damascene processes, using hard-masks to achieve vertical walls and hence smaller spaces in the damascene structures, introducing low-k (dielectric constant) insulating materials to reduce RC delays, and metallizing with copper without the deleterious effects of bridging after CMP. These are accomplished by using a novel recipe for etching the hard-masks used in a dual damascene process and still another recipe for etching low-k dielectric layers in three different combinations with oxide-based dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.