Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure
US6194265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jul 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method of creating a DRAM capacitor structure, featuring a crown shaped storage node structure, has been developed. The crown shaped storage node structure, features the formation of an hemispherical grain, (HSG), silicon layer, only on a top portion of the structure, with the bottom portion of the crown shaped storage node structure, featuring non - HSG, or smooth surfaces. This configuration is achieved via creation of a capacitor opening, in a doped oxide - undoped oxide, composite insulator layer, used as the shape for subsequent formation of an amorphous silicon crown shaped structure. Selective removal of the overlying doped oxide layer, allows selective formation of an HSG silicon layer, only on the exposed top portion of the amorphous silicon crown shaped structure. Subsequent removal of the undoped oxide layer, exposes a bottom portion of the amorphous silicon crown shaped structure, featuring non - HSG silicon surfaces, allowing easier formation of a capacitor dielectric layer, specifically at the bottom corner of the crown shaped storage node structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.