Split gate flash cell with extremely small cell size
US6194272A · kind A · utility
50Cited by
13References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 19, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | May 19, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
Abstract
A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.