VDMOS transistor protected against over-voltages between source and gate
US6194761A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jan 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
Abstract
The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.