Integrated electrical circuit having at least one memory cell and method for fabricating it

US6194765A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Hans Reisinger · Grünwald, DE
• Reinhard Stengl · Stadtbergen, DE
• Ulrike Gruning · Hopewell Junction, US
• Volker Lehmann · Hersbruck, DE
• Hermann Wendt · Grasbrunn, DE
• Josef Willer · Riemerling, DE
• Martin Franosch · Munich, DE
• Herbert Schafer · Höhenkirchen-Siegertsbrunn, DE

Key dates

• Filing date: May 17, 1999
• Grant date: Feb 27, 2001
• Expiry date: May 17, 2019

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/903

Abstract

An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.