Integrated circuit device
US6194932A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.