Stacking layers containing enclosed IC chips
US6195268A · kind A · utility
38Cited by
16References
9Claims
0Family size
Inventor
Key dates
| Filing date | Feb 26, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Feb 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is formed with a cavity in which at least one IC chip is placed, electrically connected, and then covered to enclose the chip. Full tests to establish known good quality are performed on individual layers containing enclosed chips. Within each layer horizontal conducting traces connect with conductor-containing vias, in order to carry electrical signals vertically from layer to layer, and also to connect to a ball grid array on the bottom of the stack, the entire surface of which is available for I/O ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.