Apparatus for sampling instruction execution information in a processor pipeline
US6195748A · kind A · utility
52Cited by
67References
49Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. Event, latency, and state information of the system is sampled while any of the selected instructions are in any stage of the pipeline. Software is informed whenever any of the selected instructions leaves the pipeline to read the event and latency information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.