Boundary scan latch configuration for generalized scan designs
US6195775A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Sep 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.