Constrained register sharing technique for low power VLSI design
US6195786A · kind A · utility
40Cited by
5References
7Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 3, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jun 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power management method and system targeted toward high-level synthesis of data-dominated behavioral descriptions. The method of the present invention is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, a procedure for constraining variable assignment is provided so that the functional units in the synthesized architecture do not execute any spurious operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.