Parallel test method
US6196677A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 20, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | May 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31905
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is directed to a method and system for testing a plurality of integrated circuits. According to one embodiment of the invention, a method and system for testing a plurality of integrated circuits using a probe card having a plurality of circuit sites is provided. First, a group of the plurality of integrated circuits is associated with the probe card and a first-pass test is performed in parallel on each associated integrated circuit in the group using a first number of signal channels for each circuit site. A particular one of the integrated circuits in the group which passed the first-pass tests is then selectively associated with a particular one of the circuit sites, and a second-pass test is performed on the particular one integrated circuit using a second number of signal channels greater than the first number. In this manner, the use of test system resources may be optimized with expensive second-pass tests (e.g., performance tests) only being performed on circuits passing less-expensive first-pass tests (e.g., BIST and scan tests).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.