Method for forming polycide dual gate
US6197672A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/664
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an .alpha.-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.