Semiconductor memory and method of fabricating the same
US6198122A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Feb 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A semiconductor memory includes a semiconductor substrate, a memory cell portion formed on the substrate and including stacked capacitors formed on the substrate, each having a storage electrode formed on a bottom surface of a recess in an insulating layer, a capacitor insulating film formed on the storage electrode, and a plate electrode formed on the capacitor insulating film and lower than an upper edge of the recess, and a first multilayered interconnecting layer having an interconnecting layer including a plate interconnection connected to the plate electrode, and a peripheral circuit portion formed adjacent to the memory cell portion on the substrate and comprising a second multilayered interconnecting layer. The plate interconnection includes a portion so formed as to bury the recess and connected to the plate electrode, and the second multilayered interconnecting layer includes an interconnecting layer having an upper surface substantially leveled with an upper surface of the interconnecting layer including the plate interconnection of the first multilayered interconnecting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.