Ferroelectric memory devices which utilize boosted plate line voltages to improve reading reliability and methods of operating same
US6198651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Sep 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Ferroelectric memory devices include a plate line, a bit line, a ferroelectric memory cell containing a first access transistor and a first ferroelectric capacitor electrically connected in series between the bit line and the plate line, and a word line electrically connected to a gate electrode of the first access transistor. A row decoder and a preferred plate line pulse generator are also provided to generate a write voltage of first magnitude (e.g., Vcc) on the plate line during a write time interval and a read voltage of a second magnitude (e.g., Vcc+.alpha.), greater than the first magnitude, on the plate line during a read time interval. These different magnitudes of the write and read voltage for the plate line are generated in response to a control signal (CP), so that during a read operation, the magnitude of the change in voltage across the ferroelectric capacitor will be sufficient to enable a complete charge transfer of 2Q.sub.R when the ferroelectric memory cell is storing a data 1 value. The plate line pulse generator may comprise a pulse generator, a voltage boosting circuit having an input electrically coupled to an output of the pulse generator and a switch circui…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.