Non-volatile semiconductor integrated memory device
US6198652A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Apr 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated memory device comprises a plurality of memory cell blocks, which are formed in the form of a matrix and each of which comprises: a memory cell chain including a plurality of units, each comprising a ferroelectric memory capacitor and a control transistor connected in parallel thereto; a reference capacitor of a unit comprising a reference capacitor and a control transistor connected in parallel thereto; a read transistor having a gate electrode connected to a connection point between the memory cell chain and the reference cell; and a control transistor for adjusting potentials of storage node which is a connection point of the first electrode of the memory capacitor, the third electrode of the reference capacitor and the read transistor. With this construction, the semiconductor integrated memory device is able to be easily produced, to stably retain a ferroelectric polarization and to scale down.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.