Probeless testing of pad buffers on wafer
US6199182A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The input and output buffers and related peripheral circuits, such as holding circuits and ESD circuits, of an integrated circuit are tested using the boundary scan paths and three additional test bond pads. This structure provides for testing these circuits without the need physically to contact the functional bond pads. For an output buffer, one switch opens the connection between the output of the functional circuits and the input of the output buffer. A second switch connects the first test bond pad to the input of the output buffer. A third switch connects the second test bond pad to the output of the output buffer. A fourth switch connects the third test bond pad to the output of the output buffer. For an input buffer, separate first and second switches respectively connect the second and third test bond pads to the input of the input buffer. A third switch connects the first test bond pad to the output of the input buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.