Method of fabricating self-aligned contact in embedded DRAM
US6200848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.