Method of fabricating self-aligned stacked gate flash memory cell

US6200856A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Bin Chen · Palo Alto, US

Key dates

• Filing date: Jul 28, 1998
• Grant date: Mar 13, 2001
• Expiry date: Jul 28, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

A technique for forming an integrated circuit device having a self-aligned gate layer and an overlying stacked gate. The method includes a variety of steps such as providing a substrate (217), which is commonly a silicon wafer. Field isolation regions (201) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (201) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (205) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. A stacked control gate layer is formed overlying the thickness of material.