Method and apparatus to reduce clock jitter of an on-chip clock signal
US6201448A · kind A · utility
35Cited by
12References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Dec 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An on-die clock generator. For one aspect of the invention, the on-die clock generator includes a phase-locked loop (PLL) circuit having a first input coupled to receive an external clock signal and an output coupled to provide an on-die clock signal to be used during a normal operating mode of an integrated circuit. The on-die clock generator also includes a local clock generator circuit having an input coupled to receive the on-die clock signal and an output coupled to provide a local PLL feedback clock signal to a second input of the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.