Timing circuit for high voltage testing
US6201752A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Sep 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is designed with a detector circuit (700) coupled between a supply voltage terminal (705) and a reference voltage terminal (755). The detector circuit produces a first control signal in response to a detected mode and produces a second control signal in response to another mode. A first circuit (205, 207) including a delay circuit receives the first control signal and a third control signal. The delay circuit produces a fourth control signal at an output terminal (215) in response to the first and third control signals. A second circuit (203) receives the second control signal and the third control signal. The second circuit produces the fourth control signal at the output terminal in response to the second and third control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.