Method for producing a high-voltage and low-voltage MOS transistor with salicide structure

US6204129A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Ching-Chun Hwang · Taichung, TW
• Wei-Chung Chen · Kaohsiung, TW
• Chien-Kuo Yang · Taipei, TW

Key dates

• Filing date: Oct 22, 1999
• Grant date: Mar 20, 2001
• Expiry date: Oct 22, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0142

Abstract

A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-voltage MOS transistor, which self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed over said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region. Consequently, a first photoresist layer is formed over the first dielectric layer, wherein defining and etching the first photoresist layer to form gates of high-voltage MOS and low-voltage MOS. Then, using said second photoresist layer as a mask above low-voltage MOS region, firstly implanting the substrate of the high-voltage MOS region to form conductivity-type…