Rapid thermal annealing of doped polycrystalline silicon structures formed in a single-wafer cluster tool
US6204198A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O.sub.2,O.sub.3, NO, N.sub.2 O, H.sub.2 O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer. More preferably, it has a thickness which is greater than 3 nm (more preferably greater than 2 nm). In an alternative embodiment, the thickness of the oxide layer is less than 20 nm (more preferably, less than 10 nm thick).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.