Process scheme to form controlled airgaps between interconnect lines to reduce capacitance
US6204200A · kind A · utility
264Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1998 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Apr 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming controlled airgaps (22) between metal lines (16). A two-step high density plasma (HDP) chemical vapor deposition (CVD) process is used to form the silicon dioxide dielectric layer (20) with the controlled airgaps (22). The first step involves a high gas flow and low substrate bias conditions to deposit silicon dioxide with a high deposition to sputter etch ratio. The second step uses a low gas flow and high substrate bias condition to increase the sputter component of the deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.