Dynamic random access memory structure
US6204528A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 2000 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Jan 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A dynamic random access memory structure. The structure includes a substrate having protruding sections and recessed sections, in which the protruding sections have sidewalls and a substrate surface is located between the protruding sections and the recessed sections. A gate oxide layer is formed on the sidewalls of the protruding sections and on the surfaces between the protruding sections and the recessed sections. A doped region is formed near the bottom of each protruding section, and these doped regions serve as buried bit lines. A channel region is formed in the protruding section and a gate electrode is formed on each side of the channel region. A storage electrode is connected to the other end of the protruding section and a word line is connected to the gate electrode. The word line and the buried bit line are perpendicular to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.