System and method for detecting flash memory threshold voltages
US6205057A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 15, 2000 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Feb 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a first flash memory cell, a second flash memory cell having a programmed threshold voltage, a first current sink, a second current sink, and a control circuit. The first flash memory cell is electrically interconnected with the first current sink and the controller. The second flash memory cell is interconnected with the second current sink and the controller. A method that identifies the threshold voltage range of the first memory cell monitors the current drawn from the first and the second flash memory cells and generates a signal that identifies the threshold voltage range of the first memory cell. In an alternative memory array, a first and a second current source replace the first and second current sinks, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.