Fast 2-input 32-bit domino adder
US6205463A · kind A · utility
4Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 1997 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.