Method of fabricating flash erasable programmable read only memory
US6207504A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method of fabricating flash erasable programmable read only memory. A substrate having an isolation structure is provided. A tunnel oxide layer and a floating gate layer are formed in sequence over substrate and are patterned. An ion implantation is performed and a first doped region is formed in the substrate. An oxidation step is performed to form a first oxide layer over the substrate. A nitride/oxide layer and a control gate layer are formed in sequence over the substrate. The control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer are patterned until the substrate is exposed. An ion implantation step is performed to form a common source region and a drain region in the substrate. Spacers are formed over the sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer. A self-aligned silicide step is performed to form silicide layers over the control gate layer, the common source region, and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.