Low jitter phase locked loop having a sigma delta modulator and a method thereof
US6208211A · kind A · utility
28Cited by
22References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Sep 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop PLL has a current controlled oscillator ICO, having an input resistance Rin. Rin is proportional to a control current Idac sent to ICO. ICO is coupled to a capacitor, the capacitor and Rin introduce a pole Fpole in the transfer function of PLL. The PLL further has a sigma delta modulator, for providing a digital sigma delta modulated control signal SDO, SDO is converted to an analog control current Idac, that is provided to ICO and smoothed by Rin and the capacitor. The sigma delta modulator forces error signal outside a predetermined frequency BWsd; and Fpole tracks BWsd.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.